Proposal for a Bachelor/Master Thesis at the Institute of Robotic and Embedded system Direct GPU/FPGA Communication

Systems is dealing with the challenge of providing high-performance ECUs as an enabling technology applicable in the automotive field, which will be a heterogenous system with multi-core CPU, FPGA, and GPU. A key requirement of such heterogeneous computing system is the ability to transfer data between components at high bandwidth and low latency. Several GPGPU abstractions support explicit transfers between the CPU and GPU[1, 2, 3], and it has recently been shown that this is also possible between CPU and FPGA [4]. However, the GPU-FPGA communication still relies on cumbersome approach. Existing facilities may be used to implement GPU to FPGA communication by transferring data through CPU memory as illustrated by the red line in Fig. 1. Data must traverse through the PCI Express switch twice and suffer the latency penalties of both the operating system and the CPU memory hardware using the red indirect path. We refer to this as a GPU-CPU-FPG transfer. This additional indirection adds communication latency and operating system overhead to the computation, as well as consuming bandwidth that can otherwise be used by other cluster elements sharing the same communication network. Figure 1: Conceptual Models of GPU to FPGA Transfers Therefore, our aim is to describe and evaluate a mechanism for implementing the green line in Fig. 1 for direct, bidirectional GPU-FPGA communication over the PCIe bus [5]. As illustrated, data moves through the PCIe switch once and is never copied into system memory, thus enabling more efficient communication between these disparate computing elements. We refer to this as GPU-FPGA transfer. 1 The project will include the following phases: • Investigate the current technique of GPU-FPGA communication. • Design a new GPU-FPGA communication driver for Cyclone V SoC boar