A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding

Abstract—This paper presents a fast algorithm and its VLSI ar-chitecture for H.264 fractional motion estimation. Motivated by the high correlation of cost between neighboring fractional pel po-sition, the proposed algorithm efficiently explores the neighbor-hood position around the minimum one and thus skips other un-likely ones. Thus, the proposed search pattern and early termina-tion under constant quantization parameter can reduce about 50% of computation complexity compared to that in reference software but only with 0.1–0.2 dB peak signal-to-noise ratio degradation and less than 2 % of bit rate increase. The VLSI architecture of the pro-posed algorithm thus can save 40 % of area cost due to only half of the processing elements and save 14 % of searching time when com-pared with the previous design. Index Terms—H.264/AVC, motion estimation, video coding. I