A Configurable Architecture to Limit Wakeup Current in Dynamically-Controlled Power-Gated FPGAs

A dynamically-controlled power-gated (DCPG) FPGA ar-chitecture has recently been proposed to reduce static en-ergy dissipation during idle periods. During a power mode transition from an off state to on state, the wakeup current drawn from power supplies causes a voltage droop on the power distribution network of a device. If not handled ap-propriately, this current and the associated voltage droop could cause malfunction of the design and/or the device. In DCPG FPGAs, the amount of wakeup current is not known beforehand as the structures of power-gated modules are ap-plication dependent; thus, a configurable solution is required to handle wakeup current. In this paper we propose a pro-grammable wakeup architecture for DCPG FPGAs. The proposed solution has two levels: a fixed intra-region level and a configurable inter-region level. The architecture en-sures that a power-gated module can be turned on such that the wakeup current constraints are not violated. We study the area and power overheads of the proposed solution. Our results show that the area overhead of the proposed inrush current limiting architecture is less than 2 % for a power gating region of size 3x3 or 4x4 tiles, and the leakage power saved is more than 85 % in a region of size 4x4 tiles