OSaware branch prediction: Improving microprocessor control flow prediction for operating systems

Abstract—Many modern applications have a significant operating system (OS) component. The OS execution affects various architectural states, including the dynamic branch predictions, which are widely used in today’s high-performance microprocessor designs to improve performance. This impact tends to become more significant as the designs become more deeply pipelined and more speculative. In this paper, we focus on the issues of understanding the OS effects on the branch predictions and designing architectural support to alleviate the bottlenecks that are created by misprediction. In this work, we characterize the control flow transfer of several emerging applications on a commercial OS. It was observed that the exception-driven, intermittent invocation of OS code and user/OS branch history interference increased misprediction in both user and kernel code. We propose two simple OS-aware control flow prediction techniques to alleviate the destructive impact of user/OS branch interference. The first consists of capturing separate branch correlation information for user and kernel code. The second involves using separate branch prediction tables for user and kernel code. We demonstrate in this paper that OS-aware branch predictions require minimal hardware modifications and additions. Moreover, the OS-aware branch predictions can be integrated with many existing schemes to further improve their performance. We studied the improvement contributed by OS-aware techniques to various branch prediction schemes ranging from the simple Gshare to the more advanced Agree, Multi-Hybrid, and Bi-Mode predictors. On the 32K-entry predictors, incorporating the OS-aware techniques yields up to 34 percent, 23 percent, 27 percent, and 9 percent prediction accuracy improvement on the Gshare, Multi-Hybrid, Agree, and Bi-Mode predictors, respectively. Index Terms—Pipeline processors, branch prediction, processor architectures, hardware/software interfaces, computer system implementation, performance of systems