Three kinds of timing signals, 12-MHz clock, 25-Hz trigger, and type code (control word), are used in the timing system of J-PARC. The timing signals are generated in the central control room (CCR) and are delivered to each facilities. In the klystron gallery of the linac, these signals are received, divided, and distributed to each station. However, in this distribution system, an optical signal from CCR is transformed to an electrical one by a O/E module and divided by a FANOUT module, and then re-transformed to an optical by E/O module. This system is a source of troubles such as the module failure, the timing trouble of LLRF for temperature drift and so on. Therefore, we would like to update the timing signal distribution system for use...
The present article presents a system making it possible to produce time information at spatially se...
The timing system of the KEK electron linac has been restructured for the KEKB project since a highe...
The new LLRF system architecture based on the ATCA platform was developed and tested at FLASH. The L...
In the J-PARC linac, the injection energy to the next ring was upgraded from 181MeV to 400MeV by ins...
The J-PARC 181-Mev proton linac requires twenty-four RF systems, which operate at a 620-µs pulse wid...
J-PARC is a large scale facility of the proton accelerators for the multi-purpose of scientific rese...
The present status of the design and construction of the control system for Japan Proton Accelerator...
A timing system comprising an electronic master clock and a subsystem for distributing time signals ...
Fermi is the fourth generation Light Source that is currently being designed at ELETTRA, in the fram...
This article describes recent progress of the prototype control system for the J-PARC 60-MeV proton ...
This paper describes details of the software trigger signal distribution and the reference clock sig...
The Synchronous Timing System is designed to provide sub-nanosecond timing to instrumen-tation durin...
The accelerator of the J-PARC complex consists of the 400MeV (initially 181MeV) linac, the rapid cyc...
The 2-GeV electron linac at Pohang accelerator laboratory (PAL) has been operated continuously as a ...
A separated drift tube linac (SDTL) was adopted as an accelerating structure of Japan Proton Acceler...
The present article presents a system making it possible to produce time information at spatially se...
The timing system of the KEK electron linac has been restructured for the KEKB project since a highe...
The new LLRF system architecture based on the ATCA platform was developed and tested at FLASH. The L...
In the J-PARC linac, the injection energy to the next ring was upgraded from 181MeV to 400MeV by ins...
The J-PARC 181-Mev proton linac requires twenty-four RF systems, which operate at a 620-µs pulse wid...
J-PARC is a large scale facility of the proton accelerators for the multi-purpose of scientific rese...
The present status of the design and construction of the control system for Japan Proton Accelerator...
A timing system comprising an electronic master clock and a subsystem for distributing time signals ...
Fermi is the fourth generation Light Source that is currently being designed at ELETTRA, in the fram...
This article describes recent progress of the prototype control system for the J-PARC 60-MeV proton ...
This paper describes details of the software trigger signal distribution and the reference clock sig...
The Synchronous Timing System is designed to provide sub-nanosecond timing to instrumen-tation durin...
The accelerator of the J-PARC complex consists of the 400MeV (initially 181MeV) linac, the rapid cyc...
The 2-GeV electron linac at Pohang accelerator laboratory (PAL) has been operated continuously as a ...
A separated drift tube linac (SDTL) was adopted as an accelerating structure of Japan Proton Acceler...
The present article presents a system making it possible to produce time information at spatially se...
The timing system of the KEK electron linac has been restructured for the KEKB project since a highe...
The new LLRF system architecture based on the ATCA platform was developed and tested at FLASH. The L...