Improving logic density through synthesisinspired architecture

We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved logic density. We demonstrate that an “extended ” logic el-ement with slightly modified K-input LUTs achieves much of the benefit of an architecture with K+1-input LUTs, while consuming silicon area close to a K-LUT (a K-LUT re-quires half the area of a K+1-LUT). We introduce the notion of “non-inverting paths ” in a circuit’s AND-inverter graph (AIG) and show their utility in mapping into the proposed logic element. Results show that while circuits mapped to a traditional 5-LUT architecture need 14 % more LUTs and have 12 % more depth than a 6-LUT architecture, our ex-tended 5-LUT architecture requires only 7 % more LUTs and 2.5 % more depth than 6-LUTs, on average. Nearly all of the depth reduction associated with moving from K-input to K+1-input LUTs can be achieved with considerably less area using extended K-LUTs. We further show that 6-LUT optimal mapping depths can be achieved with a small frac-tion of the LUTs in hardware being 6-LUTs and the remain-der being extended 5-LUTs, suggesting that a heterogeneous logic block architecture may prove to be advantageous. 1