Full-Wafer, Small-Area Via-Hole Fabrication Process Development for Indium- Bearing III-V Heterostructure Devices

Comparison of several process alternatives for forming small-area, high-density vias in Indium-bearing III-V materials by dry etching is presented. While through-wafer via etches are well-established in production, as MMIC operational frequencies increase there is an increasing need for high-density, small-area vias for grounding active devices and suppressing substrate modes. In addition, less conventional devices such as InGaP/GaAs/InGaAs inverted metamorphic (IMM) triple junction backside contact photovoltaic cells can also benefit from the ability to form small-area vias in dense arrays [1]. For all of these applications, strongly anisotropic etch profiles are necessary to minimize via area (see Fig. 1 for an example of vias as applied to a backside contact photovoltaic cell). To serve these needs, a study of three different dry etch chemistries (Cl2/Ar, BCl3/Cl2/Ar, and SiCl4/Ar) is reported, and a process based on SiCl4/Ar that results in very smooth sidewalls with good etch profiles has been identified. For the process development shown here, vias were formed in triple-junction solar cell epitaxial material (see Fig. 1 for details). This places extreme demands on the via fabrication process, since straight sidewalls through materials with widely varying composition (especially In content) is challenging. The processes shown here can be translated to the simpler case of single-material vias with minor tuning. The process development was carried out in an Oerlikon Shuttleline inductively coupled plasma reactive ion etching (ICP-RIE) system with helium backside cooling. A SiO2 layer was used as the hard mask. To provide improved process monitoring and robustness, optical emission spectroscopy (OES