FPGA glitch power analysis and reduction

Abstract—This paper presents a don’t-care-based synthesis technique for reducing glitch power in FPGAs. First, an analysis of glitch power and don’t-cares in a commercial FPGA is given, showing that glitch power comprises an average of 26.0 % of total dynamic power. An algorithm for glitch reduction is then presented, which takes advantage of don’t-cares in the circuit by setting their values based on the circuit’s simulated glitch behavior. Glitch power is reduced by up to 49.0%, with an average of 13.7%, while total dynamic power is reduced by up to 12.5%, with an average of 4.0%. The algorithm is applied after placement and routing, and has zero area and performance overhead. Index Terms – FPGA, glitch power, don’t-cares, SAT I