Effect of Pulsed Stress on Leakage Current In MOS Capacitors For Non-Volatile Memory Applications

A detailed investigation of leakage current in MOS capacitors under pulsed electrical stress is presented. In particular the effect of pulse amplitude, pulse width, time between two pulses and stress temperature is studied. A new model of trap kinetics is discussed, based on the assumption that electrical stress induces creation of both stable and metastable states (trap precursors). The latter states are not involved in trap-assisted-tunnel transport and therefore do not contribute to stress induced leakage current (SILC). However, precursors can anneal spontaneously, if the external perturbation is removed, or convert into stable traps, if the electrical stress lasts for a sufficient time. Experimental data of SILC in pulsed regime are coherently interpreted within the frame of this model