A Modified Hardware-Efficient H.264/AVC Motion Estimation Using Adaptive Computation Aware Algorithm

Abstract- In order to increase transmission efficiency of the real world video sequences, Motion estimation (2) plays an vital role. An improved version of the reconfigurable block motion estimation algorithm (3) is proposed in this paper. The new algorithm uses a small cross-shaped search patterns to speed up the motion estimation of stationary and quasi- stationary blocks. Also we propose a pipelining method for SAD unit to minimize clock delays with minimum area overhead. Our approach increases speed and enhance the throughput for Codec design. We propose a new method “Block Motions matching technique (BMM) ” (2) where compression takes place at both Spatial and Temporal domain. In BMM, images are sub divided into micro blocks of 16x16 matrices and it is checked with nearby blocks. Also this method is applied for video compression techniques. The advantage of BMM over existing system is that it compresses block level compression instead of pixel level compression that improves execution speed and adapt for fast processing. Index Terms- Field-programmable gate array (FPGA), H.264/AVC, motion estimation, multipath search algorithm very large-scale integration (VLSI) architecture, video coding. I