Server I/O Acceleration Using an Embedded Multi-core Architecture

This paper presents a feasibility study on the use of an embedded multi-core system-on-a-chip (SoC) architecture to accelerate server I/O subsystem functions, as an alternative to implementation via finite state machines (FSMs) and hardwired logic. The multi-core solution is significantly more programmable than FSMs and avoids many of their shortcomings. For the purposes of this SoC we use the Cyclops scalable embedded multiprocessor architecture (CyclopsE) that comprises one or more processor clusters, one or more local memory banks for storing data and/or instructions, and a local interconnect implemented via a crossbar switch. The I/O functionality was implemented in C language and verified on an FPGA-based prototype that emulated a server I/O subsystem handling storage area network traffic. Results showed that for the higher-level protocols of interest, a modest number of processor cores are sufficient to handle traffic up to 8 Gb/s. Given the small silicon area and power requirements as well as good scalability of CyclopsE, much higher bandwidths can be accommodated with the use of larger numbers of cores