Automated Extraction of Hardware Accelerators Via an Intelligent

doi:10.4156/ijiip.vol1. issue2.2 Due to the increased complexity of modern embedded applications and integrated circuits there has been a long effort for automated techniques and tools to automatically produce correct hardware and systems from high-level, abstract and executable specifications written in a contemporary programming language. Furthermore, the automatically produced hardware modules of the embedded system can act as hardware accelerators that speed-up certain system tasks. This paper describes an intelligent, knowledge-based system (IKBS), which is used as an automated design framework for verified and correct hardware accelerators. The IKBS design framework transforms a number of Prolog predicate facts into a number of verified hardware modules, via its inference engine’s logic rules. The predicate facts are produced automatically via a front-end compiler and directly from high-level algorithmic program code specification models. The produced hardware accelerators are extracted as a number of functionally standalone FSM-controlled data processing accelerators. The IKBS is implemented with a great number of logic rules that associate a number of predicates with another predicate in the form of a logic relation-production rule. The generated hardware accelerators are implemented directly into VLSI technology (e.g. FPGAs or ASICs) using standard industrial ECAD tools. Experimental results demonstrate that the high-level program to hardware accelerator transformation is formal and correct, and the initial extracted control states are reduced significantly using a parallelizing scheduling algorithm, which is embedded into the IKBS rules. Statistics with a number of real-life applications, including an MPEG engine, show the usability and benefits of the presented, system-design approach