PROVIDING MULTIPLE SUPERSCALAR CORE TYPES ON A CHIP, EACH TAILORED TO DIFFERENT CLASSES OF INSTRUCTION-LEVEL BEHAVIOR, IS AN EXCITING DIRECTION FOR INCREASING PROCESSOR PERFORMANCE AND ENERGY EFFICIENCY. UNFORTUNATELY, PROCESSOR DESIGN AND VERIFICATION EF

......The past decade has witnessed a major transition from single-core to multi-core processors. Multicore processors present an exciting opportunity to exploit diversity within and across applications by employing microarchitecturally diverse superscalar core types, in what is called a single-instruction-set architecture (single-ISA) heterogeneous multicore processor.1 Program phases differ in their instruction-level characteristics: the amount and distribution of instruction-level parallelism (ILP) and memory-level parallel-ism (MLP), branch predictability, and cache locality. We can improve performance and power metrics by matching instruction