Impact of Dynamic Voltage Frequency Scaling on the Architectural Vulnerability of GALS Architectures

Aggressive technology scaling is increasing the impact of soft errors on microprocessor reliability. Dynamic Voltage Fre-quency Scaling (DFVS) algorithms are conventionally stud-ied from a performance per watt basis. But applying DVFS impacts reliability as well. Since DVFS affects the occu-pancy of different pipeline structures, they impact the soft error masking seen at the architectural level. Architectural Vulnerability Factors (AVF) captures this masking and in this work we study the impact of DVFS on AVF in a GALS environment. We show that the AVF of pipeline structures could vary by as much as 80 % between different DVFS al-gorithms. Since AVF has a significant impact on the Mean Time To Failure (MTTF) of a system, these results indi-cate that when choosing a particular DVFS algorithm their reliability impact cannot be ignored. Hence we provide the Vulnerability Efficiency for the DVFS algorithms which cap-tures their ability to optimize performance, power and relia-bility. Our results show that a Non-DVFS environment op-timizes vulnerability efficiency better than any of the DVFS algorithms