REDUNDANCY AND PARALLELISM TRADEOFFS FOR RELIABLE, HIGH-PERFORMANCE ARCHITECTURES

For decades, high performance processors have provided architectural and microar-chitectural abstractions that enable applications to exploit parallelism as a means to fruitfully utilize the exponentially increasing on-chip transistor counts. With shrinking device sizes, reduced supply voltages and growing integration densities leading to logic elements becoming increasingly susceptible to transient faults, re-search works have established techniques to leverage existing on-chip parallelism-targeted abstractions to provide redundancy for processor pipelines, thereby increasing their resilience to transient faults. While prior works have viewed the impact of provisioning such redundancy as performance and/or implementation costs, this thesis attempts to: establish the view that there exists a fundamental tradeoff between parallelism and redundancy, propose ecient mechanisms that can be built to enable processor cores t