A quantitative study on performance-power impact of dualspeed pipeline architectures

The drastic increase in power consumption by modern processors emphasizes the need for power-performance trade-offs in architecture design space exploration and compiler optimizations. This paper reports a quantitative study on the power-performance trade-offs in software pipelined schedules for an Itanium-like EPIC architecture with dual-speed pipelines, in which functional units are partitioned into fast ones and slow ones. We have developed an integer linear programming formulation to capture the energy/performance tradeos for software pipelined loops. The proposed integer linear programming formulation and its so-lution method have been implemented and tested on a set of SPEC2000 benchmarks. The results are compared with an Itanium-like architecture(baseline) in which there are four functional units(FUs) and all of them are fast units. Our quantitative study reveals: 1. There is considerable energy saving by introducing a few slow FUs in place of fast FUs in the baseline architecture. When 2 out 4 FUs are set as slow, the total energy consumed by FUs is reduced by up to 31.1 % (with an average reduction of 25.2%