OF 3,930 DMIPS/W.

sors contain billions of devices per chip.1 Meanwhile, global interconnect hasn’t kept pace, because global wires scale in only one dimension instead of two, resulting in fewer, high-resistance routing tracks. Because of this problem and increasing design complexity, the industry is moving toward system-on-chip (SoC) designs or chip multi-processors (CMPs). In these designs, multi-ple components share the same die, as opposed to one giant processor occupying it entirely. These systems typically include processing cores, memory controllers, video decoders, and other application-specific inte-grated circuits (ASICs)