A Scalable Memory-Efcient Architecture for Parallel Shared Memory Switches

AbstractParallel shared memory (PSM) switch architectures were initially introduced as means of resolving the high memory bandwidth requirements imposed by output-queued switches. At the core of the PSM architecture is a memory management algorithm that determines, for each arriving packet, the memory unit in which it will be placed. Recent work has indicated that in order to achieve high throughput, the number of parallel memo-ries needed is O N1:5; thereby signicantly limiting scalability. This paper introduces a novel pipelined memory management algorithm which maintains a computational complexity of O (1) while reducing the number of required parallel memories to O (N). Our goal is to extend existing shared-memory architecture results in the context of Fabric on a Chip (FoC)- a paradigm that advocates the consolidation of core packet switching functions on a single chip. A detailed discussion is provided pertaining to the fundamental properties of the proposed scheme, along with hardware implementation considerations that illustrate its scalability and performance attributes. I