Abstract—We propose a method that prevents single event latchup (SEL) using deep P-well on P-substrate. To confirm the effectiveness of the proposed method, SEL and single event upset (SEU) are evaluated for three well configurations; double-well, ordinary triple-well and the proposed deep P-well on P-substrate. Neutron irradiation test shows that the proposed method achieves SEL prevention without SEU increase
In radioactive environments, particle strikes can induce transient errors in integrated circuits (IC...
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover f...
This invention is comprised of a logical memory latch and cell, using logic and circuit modification...
Abstract—This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi-bit-latch (MB...
This final year project develops a new Radiation-Hardened-By-Design approach to detect Single Event ...
The focus of this thesis is single event effects in electronic circuits, and mainly single event lat...
Abstract: A single event upset (SEU) tolerant latchwith a triple-interlocked structure is presented....
In this paper, we report a novel reliability issue, coined single-event-induced barrier lowering (SE...
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A ...
ISBN: 0769524060Various fault tolerant techniques can be employed to mitigate SEUs, SETs and SELs. H...
0-7695-2620-9Single-event latchup is one of the most threatening single event effects as the induced...
A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wr...
A test program designed to verify that neutron irradiation and subsequent anneal is an effective met...
International audienceIn deep nano-scale and high-integration CMOS technologies, storage circuits ha...
heavy ion beams from their 88-inch Cyclotron. The SRAM was shown to be immune to single event latchu...
In radioactive environments, particle strikes can induce transient errors in integrated circuits (IC...
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover f...
This invention is comprised of a logical memory latch and cell, using logic and circuit modification...
Abstract—This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi-bit-latch (MB...
This final year project develops a new Radiation-Hardened-By-Design approach to detect Single Event ...
The focus of this thesis is single event effects in electronic circuits, and mainly single event lat...
Abstract: A single event upset (SEU) tolerant latchwith a triple-interlocked structure is presented....
In this paper, we report a novel reliability issue, coined single-event-induced barrier lowering (SE...
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A ...
ISBN: 0769524060Various fault tolerant techniques can be employed to mitigate SEUs, SETs and SELs. H...
0-7695-2620-9Single-event latchup is one of the most threatening single event effects as the induced...
A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wr...
A test program designed to verify that neutron irradiation and subsequent anneal is an effective met...
International audienceIn deep nano-scale and high-integration CMOS technologies, storage circuits ha...
heavy ion beams from their 88-inch Cyclotron. The SRAM was shown to be immune to single event latchu...
In radioactive environments, particle strikes can induce transient errors in integrated circuits (IC...
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover f...
This invention is comprised of a logical memory latch and cell, using logic and circuit modification...