Delta-Sigma FDC Based Fractional- PLLs

Abstract—Fractional- phase-locked loop frequency syn-thesizers based on time-to-digital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps (-PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase noise and spurious tone performance below that of the best comparable-PLLs. An alternative approach is to use a delta-sigma frequency-to-digital converter ( FDC) in place of a TDC to retain the benefits of TDC-PLLs and-PLLs. This paper proposes a practical FDC based PLL in which the quantization noise is equivalent to that of a-PLL. It presents a linearized model of the PLL, design criteria to avoid spurious tones in the FDC quantization noise, and a design method-ology for choosing the loop parameters in terms of standard PLL target specifications. Index Terms—Delta-sigma, fractional-, frequency discrim-inator, frequency synthesizers, phase-locked loop, phase noise