Achieving predictable performance through better memory controller placement in many-core CMPs

In the near term, Moore’s law will continue to provide an in-creasing number of transistors and therefore an increasing num-ber of on-chip cores. Limited pin bandwidth prevents the integra-tion of a large number of memory controllers on-chip. With many cores, and few memory controllers, where to locate the memory controllers in the on-chip interconnection fabric becomes an im-portant and as yet unexplored question. In this paper, we show how the location of the memory controllers can reduce contention (hot spots) in the on-chip fabric, as well as lower the variance in reference latency which provides for predictable performance of memory-intensive applications regardless of the processing core on which a thread is scheduled. We explore the design space of on-chip fabrics to find optimal memory controller placement relative to different topologies (i.e. mesh and torus), routing algorithms, and workloads