Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture

The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained al-most constant, making memory latency the performance bottle-neck in today’s systems. We observe that the high access la-tency is not intrinsic to DRAM, but a trade-oU made to decrease cost-per-bit. To mitigate the high area overhead of DRAM sens-ing structures, commodity DRAMs connect many DRAM cells to each sense-ampliVer through a wire called a bitline. These bit-lines have a high parasitic capacitance due to their long length, and this bitline capacitance is the dominant source of DRAM la-tency. Specialized low-latency DRAMs use shorter bitlines with fewer cells, but have a higher cost-per-bit due to greater sense-ampliVer area overhead. In this work, we introduce Tiered-Latency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit. In TL-DRAM, each long bitline is split into two shorter segments by an isolation transistor, allowing one segment to be accessed with the latency of a short-bitline DRAM without incurring high cost-per-bit. We propose mechanisms that use the low-latency segment as a hardware-managed or software-managed cache. Evaluations show that our proposed mechanisms improve both performance and energy-eXciency for both single-core and multi-programmed workloads.