An adaptive pattern recognition hardware with on-chip shift registerbased partial reconfiguration

A pattern recognition system that can process a large amount of image data at high speed is required in many fields. In this paper, we propose an on-chip pattern recognition system that utilizes the reconfig-urability of the FPGA. The features of the system are not only very high recognition speed but also an adap-tive function. For example, when objects to be de-tected change appearance, recognition parameters must be changed to retain the recognition accuracy. The system can automatically adjust by executing on-chip partial reconfiguration. The system runs at 25MHz and can return a recognition result in one clock cycle, 40ns. To update the system, all processes needed for searching for the best recognition parameters, gener-ating configuration data and reconfiguring the system are carried out within 30s. 1