Physical Layer Analysis and Modeling of Silicon Photonic WDM Bus Architectures

Silicon photonic single mode links employing dense wavelength-division multiplexing (WDM) offer a large bandwidth-distance product, high bandwidth density, and potential for close integration with compute logic leveraging CMOS-compatible fabrication processes. These unique characteristics open a new and large design space for compute-systems ’ interconnects. This work analyzes several architectures in that design space, involving multiple on-chip data-transmitting sites organized around a photonic bus waveguide. We determine the maximum feasible bandwidth of these architectures through a comprehensive analysis of the optical power budget. We also estimate their power consumption and analyze the efficiency of the designs. The results indicate scalability of such links to Tb/s but at the same time illustrate and quantify an inherent trade-off between link complexity and the maximum achievable bandwidth