Power-Aware NoCs through Routing and Topology Reconfiguration

With the advent of multicore processors and system-on-chip designs, intra-chip communication demands have exacerbated, leading to a grow-ing adoption of scalable networks-on-chip (NoCs) as the interconnect fabric. Today, conventional NoC designs may consume up to 30% of the entire chip’s power budget, in large part due to leakage power. In this work, we address this issue by proposing Panthre: our solu-tion deploys power-gating to provide long intervals of uninterrupted sleep to selected units. Packets that would normally use power-gated components are steered away via topology and routing reconfigura-tion, while Panthre provides low-latency alternate paths to their desti-nations. The routing reconfiguration operates in a distributed fashion and guarantees that deadlock-free routes are available at all times. At runtime, Panthre adapts to the application’s communication patterns by updating its power-gating decisions. It employs a feedback-based distributed mechanism to control the amount of sleeping components and of packets detours, so that performance degradation is kept at a minimum. Our design is flexible, providing a mechanism that design-ers can use to tradeoff power savings with performance, based on ap-plication’s requirements. Our experiments on multi-programmed communication-light work-loads from the SPEC CPU2006 suite show that Panthre reduces total network power consumption by 14.5 % on average, with only a 1.8% degradation in performance, when all processor nodes are active. At times when 15-25 % of the processor cores are communication-idle, Panthre enables leakage power savings of 36.9 % on average, while still providing connected and deadlock-free routes for all other nodes