Picoserver: using 3d stacking technology to enable a compact energy efficient chip multiprocessor

In this paper, we show how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multi-processor suitable for throughput processing. Our proposed archi-tecture, PicoServer, employs 3D technology to bond one die con-taining several simple slow processing cores to multiple DRAM dies sufficient for a primary memory. The 3D technology also enables wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency in turn reduces power and means that ther-mal constraints, a concern with 3D stacking, are easily satisfied. The PicoServer architecture specifically targets Tier 1 server ap-plications, which exhibit a high degree of thread level parallelism