Modeling and verifying circuits using generalized relative timing

We propose a novel technique for modeling and verify-ing timed circuits based on the notion of generalized rela-tive timing. Generalized relative timing constraints can ex-press not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using generalized relative timing constraints are formally encoded as timed automata. Novel fully symbolic verifica-tion algorithms for timed automata are then used to ei-ther verify a temporal logic property or to check confor-mance against an untimed specification. The combination of our new modeling technique with fully symbolic verification methods enables us to verify larger circuits than has been possible with other approaches. We present case stud-ies to demonstrate our approach, including a self-timed circuit used in the integer unit of the Intel R Pentium R 4 processor