With the proliferation of benchmarks available today, benchmarking new designs can significantly impact overall development time. In order to fully test and represent a typical workload, a large number of benchmarks must be run, and while current techniques such as SimPoint and SMARTS have had considerable success reducing simulation time, there are still areas of improvement. This paper details a methodology that continues to decrease this simulation time by analyzing and augmenting benchmark binaries to contain intrinsic checkpoints that allow for the rapid execution of important portions of code thereby removing the need for explicit checkpointing support. In addition, these modified binaries have increased portability across multiple si...
Checkpointing is widely used in robust fault-tolerant applications. We present an efficient incremen...
Multiple threads running in a single, shared address space is a simple model for writing parallel pr...
Time warp discrete event simulators take advantage of the parallel processing of simulation events. ...
This paper introduces a methodology to reduce the overall simulation time of large benchmarking suit...
As systems become more complex, conducting cycleaccurate simulation experiments becomes more time co...
In this paper we present a software approach, namely Fast-software-Checkpointing (FSC), to reduce th...
Data processing applications of the ATLAS experiment, such as event simulation and reconstruction, s...
This paper describes a non-blocking checkpointing mode in support of optimistic parallel discrete e...
Next-generation exascale systems, those capable of performing a quintillion operations per second, ...
As time goes on, hardware designs get ever more complicated, and producing designs that work properl...
Next-generation exascale systems, those capable of performing a quintillion (10{sup 18}) operations ...
The large scale of current and next-generation massively parallel processing (MPP) systems presents ...
We acknowledge funding by the EPSRC grant PAMELA EP/K008730/1.Full-system simulators are increasingl...
Full-system simulators are increasingly finding their way into the consumer space for the purposes o...
Great effort has been devoted to the design of optimized checkpointing strategies for optimistic par...
Checkpointing is widely used in robust fault-tolerant applications. We present an efficient incremen...
Multiple threads running in a single, shared address space is a simple model for writing parallel pr...
Time warp discrete event simulators take advantage of the parallel processing of simulation events. ...
This paper introduces a methodology to reduce the overall simulation time of large benchmarking suit...
As systems become more complex, conducting cycleaccurate simulation experiments becomes more time co...
In this paper we present a software approach, namely Fast-software-Checkpointing (FSC), to reduce th...
Data processing applications of the ATLAS experiment, such as event simulation and reconstruction, s...
This paper describes a non-blocking checkpointing mode in support of optimistic parallel discrete e...
Next-generation exascale systems, those capable of performing a quintillion operations per second, ...
As time goes on, hardware designs get ever more complicated, and producing designs that work properl...
Next-generation exascale systems, those capable of performing a quintillion (10{sup 18}) operations ...
The large scale of current and next-generation massively parallel processing (MPP) systems presents ...
We acknowledge funding by the EPSRC grant PAMELA EP/K008730/1.Full-system simulators are increasingl...
Full-system simulators are increasingly finding their way into the consumer space for the purposes o...
Great effort has been devoted to the design of optimized checkpointing strategies for optimistic par...
Checkpointing is widely used in robust fault-tolerant applications. We present an efficient incremen...
Multiple threads running in a single, shared address space is a simple model for writing parallel pr...
Time warp discrete event simulators take advantage of the parallel processing of simulation events. ...