Add to ORKGIn this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18µm technology. The processor employs a delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44 % energy savings over the worst case operating conditions for a 0.1 % targeted error rate at a fixed frequency of 120MHz. 1
This paper discusses a timing error masking-aware ARM Cortex M0 microcontroller system. Through in-p...
This paper presents the first known timing-error detection (TED) microprocessor able to operate in s...
International audienceAn efficient implementation of voltage over-scaling policies for ultra-low pow...
Abstract—In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which inco...
Abstract—In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which inco...
Abstract—Traditional adaptive methods that compensate for PVT variations need safety margins and can...
Rising PVT variations at advanced process nodes make it increasingly difficult to meet aggressive pe...
textThe Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing perfor...
DVS (Dynamic Voltage Scaling) is a technique used for reducing the power consumption of digital cir...
Energy per operation minimum can be reached, depending on the process node, at near- or subthreshold...
Low-power consumption has become an important aspect of processors and systems design. Many techniqu...
On-chip buses are typically designed to meet performance constraints at worst-case conditions, inclu...
Razor [1-3] is a hybrid technique for dynamic detection and correction of timing errors. A combinati...
This work introduces a Tunable Error Detection & Correction strategy (TED-C) aimed at improving the ...
capable of executing arbitrary DSP algorithms using fine grained Dynamic Voltage Scaling (DVS) at th...
This paper discusses a timing error masking-aware ARM Cortex M0 microcontroller system. Through in-p...
This paper presents the first known timing-error detection (TED) microprocessor able to operate in s...
International audienceAn efficient implementation of voltage over-scaling policies for ultra-low pow...
Abstract—In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which inco...
Abstract—In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which inco...
Abstract—Traditional adaptive methods that compensate for PVT variations need safety margins and can...
Rising PVT variations at advanced process nodes make it increasingly difficult to meet aggressive pe...
textThe Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing perfor...
DVS (Dynamic Voltage Scaling) is a technique used for reducing the power consumption of digital cir...
Energy per operation minimum can be reached, depending on the process node, at near- or subthreshold...
Low-power consumption has become an important aspect of processors and systems design. Many techniqu...
On-chip buses are typically designed to meet performance constraints at worst-case conditions, inclu...
Razor [1-3] is a hybrid technique for dynamic detection and correction of timing errors. A combinati...
This work introduces a Tunable Error Detection & Correction strategy (TED-C) aimed at improving the ...
capable of executing arbitrary DSP algorithms using fine grained Dynamic Voltage Scaling (DVS) at th...
This paper discusses a timing error masking-aware ARM Cortex M0 microcontroller system. Through in-p...
This paper presents the first known timing-error detection (TED) microprocessor able to operate in s...
International audienceAn efficient implementation of voltage over-scaling policies for ultra-low pow...