A baseband processor for software defined radio terminals

Software defined radio (SDR) is a technical effort to use programmable hardware in wireless communication systems so that various protocols can be easily supported by software. However, using programmable hardware for SDR terminals has been unachievable because of their tight power budget and high demand on computation capability. The main theme of this thesis is to design a power efficient programmable baseband processor for the SDR. This thesis analyzed most contemporary wireless communication protocols both in system and algorithm levels. System level analysis is to see the interactions be-tween algorithms and the algorithm level analysis is to investigate the computation patterns of the algorithms comprising baseband operations. Based on the characterization results, this thesis proposes chip multiprocessor architecture, whose PEs have both parallel and scalar datapaths. Multiprocessor architecture is proposed to exploit the algorithm level parallelism. Both the par-allel and scalar datapaths are used because baseband processing is a combination of parallelizable and scalar computations. For additional enhancements, three nove