Software-based path delay fault testing (SPDFT) has been used to identify faulty chips that cannot meet timing constraints due to gross delay defects. In this paper, we propose using SPDFT for a new purpose – aggressively selecting the operat-ing point of a variation-affected design. In order to use SPDFT for this purpose, test routines must provide high coverage of potentially-critical paths and must have low dynamic perfor-mance overhead. We describe how to apply SPDFT for select-ing an energy-efficient operating point for a variation-affected processor and demonstrate that our test routines achieve ample coverage and low overhead. 1
The delay fault test pattern set generated by timing unaware com-mercial ATPG tools mostly affects v...
Min delay violations are traditionally not modeled as possible faults as a result of manufacturing d...
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing...
International audienceNew semiconductor technologies for advanced applications are more prone to def...
International audienceWith the advance in silicon technology, the increasingly strict timing require...
New semiconductor technologies for advanced applications are more prone to defects and imperfection...
Path selection and generating tests for small delay faults is an important issue in the delay fault ...
The semiconductor industry has widely accepted transition delay fault (TDF) and path delay fault (PD...
some design disciplines have been adopted. For example, the level-sensitive scan design discip-line ...
In current technologies (65nm and beyond), functional failures caused by shorts, opens, and stuck-at...
Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a ...
Technology scaling and manufacturing process affect the performance of digital circuits, making them...
The delay fault test pattern set generated by timing unaware com-mercial ATPG tools mostly affects v...
Min delay violations are traditionally not modeled as possible faults as a result of manufacturing d...
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing...
International audienceNew semiconductor technologies for advanced applications are more prone to def...
International audienceWith the advance in silicon technology, the increasingly strict timing require...
New semiconductor technologies for advanced applications are more prone to defects and imperfection...
Path selection and generating tests for small delay faults is an important issue in the delay fault ...
The semiconductor industry has widely accepted transition delay fault (TDF) and path delay fault (PD...
some design disciplines have been adopted. For example, the level-sensitive scan design discip-line ...
In current technologies (65nm and beyond), functional failures caused by shorts, opens, and stuck-at...
Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a ...
Technology scaling and manufacturing process affect the performance of digital circuits, making them...
The delay fault test pattern set generated by timing unaware com-mercial ATPG tools mostly affects v...
Min delay violations are traditionally not modeled as possible faults as a result of manufacturing d...
textThe rapidly evolving process technologies and device complexity that have fueled the exponentia...