Abstract. Executable formal specication can allow engineers to test (or simulate) the specied system on concrete data before the system is implemented. This is beginning to gain acceptance and is just the formal analogue of the standard practice of building simulators in conventional programming languages such as C. A largely unexplored but potentially very useful next step is symbolic simulation, the \execution " of the formal speci cation on indeterminant data. With the right interface, this need not require much additional training of the engineers using the tool. It allows many tests to be collapsed into one. Furthermore, it familiarizes the working engineer with the abstractions and notation used in the design, thus allowing team ...
Methods for formal specification have been studied and evaluated in the academic environments alread...
This paper presents a software tool for generat-ing graphical interfaces for general-purpose ACSL si...
ISBN 2-913329-73-XTo satisfy market requirements, formal verification tools must allow designers to ...
This paper examines some of the roles that symbolic computation plays in assisting system-level simu...
International audienceWe use symbolic simulation for the verification of high level circuit specific...
Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a r...
This paper describes the development of progressively more powerful and abstract hardware simulators...
International audienceACL2 is a theorem prover to reason about specifications written in a quantifie...
International audienceWe present the status of an on-going work aiming at introducing symbolic simul...
Abstract − The paper deals with a symbolic simulator we have developed. It has been used as a suppor...
ISBN: 076950843XWe define the semantics of a synthesizable VHDL subset in a quantifier-free, first-o...
AbstractThis paper proposes an intermediate approach between simulation and formal verification. Thi...
Symbolic simulation is an important technique used informal property verification and test generatio...
As computer power has increased, so has the capability of software developers to write programs that...
ISBN : 978-1-4244-3341-4International audienceThis paper describes VSYML, a symbolic simulator that ...
Methods for formal specification have been studied and evaluated in the academic environments alread...
This paper presents a software tool for generat-ing graphical interfaces for general-purpose ACSL si...
ISBN 2-913329-73-XTo satisfy market requirements, formal verification tools must allow designers to ...
This paper examines some of the roles that symbolic computation plays in assisting system-level simu...
International audienceWe use symbolic simulation for the verification of high level circuit specific...
Symbolic simulation involves evaluating circuit behavior using special symbolic values to encode a r...
This paper describes the development of progressively more powerful and abstract hardware simulators...
International audienceACL2 is a theorem prover to reason about specifications written in a quantifie...
International audienceWe present the status of an on-going work aiming at introducing symbolic simul...
Abstract − The paper deals with a symbolic simulator we have developed. It has been used as a suppor...
ISBN: 076950843XWe define the semantics of a synthesizable VHDL subset in a quantifier-free, first-o...
AbstractThis paper proposes an intermediate approach between simulation and formal verification. Thi...
Symbolic simulation is an important technique used informal property verification and test generatio...
As computer power has increased, so has the capability of software developers to write programs that...
ISBN : 978-1-4244-3341-4International audienceThis paper describes VSYML, a symbolic simulator that ...
Methods for formal specification have been studied and evaluated in the academic environments alread...
This paper presents a software tool for generat-ing graphical interfaces for general-purpose ACSL si...
ISBN 2-913329-73-XTo satisfy market requirements, formal verification tools must allow designers to ...