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Abstract — Synchronizers play a key role in multi-clock domains systems on chip and their performance is usually measured by the MTBF of the system. Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling of circuits in 65nm and below. This degradation of parameters becomes critical when the system is operated at extreme supply voltage and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature conditions. A new model for the metastability time constant (τ), the metastability window (TW) and MTBF is presented. We show a detailed comparison of model, measurements and simulations for different technology nodes and discuss implications for modern synchronization systems. We propose design guidelines that account for supply voltage and temperature variations and determine the correct number of synchronizer stages required for target MTBF. Index Terms — Measurement method, metastability, MTBF