MICROPROCESSOR-CONTROLLED PERMUTATION DECODING OF

Microprocessors can be used to simplify the hardware required to build the decoder of a block error-control system, but only at the expense of the low data throughput rates characteristic of software implementation. This paper proposes a new soft-decision permutation decoding algorithm for cyclic block codes, and deals with the implementation of both hard and soft-decision permutation decoding on an Intel 8080A microprocessor system. In particular, coding gain and data throughput trade-offs are investigated for both total software and software plus specialised hard-ware implementations, under Gaussian noise conditions. Finally, possible system developments for achieving higher throughput speeds are discussed. 1