Add to ORKG512 DQ pins has been developed with 50 nm technology. It ex-hibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify functions through micro bumps and test pads have been developed. Block based dual period refresh scheme is applied to re-duce self refresh current with minimum chip size burden. Stacking of 2 dies with 7.5 m diameter and 40 m pitch TSVs has been fabricated and tested, which results in 76 % overall package yield without difference in performances between top and bottom die. Index Terms—CMOS memory integrated circuits, DRAM chips, through-silicon vias
In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for ...
A leading edge 130 mn generation logic technology with 6 layers of dual damascene Cu interconnects i...
3D TSV (through silicon via) technologies promise increased system integration at lower cost and red...
Mobile DRAM is widely employed in portable electronic devices due to its fea-ture of low power consu...
none8Convergence of communication, consumer applications and computing within mobile systems pushes ...
Abstract—In recent few years, low-power electronics has been a leading drive for technology developm...
none43D integration based on TSV (through silicon via) technology enables stacking of multiple memor...
A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-mu...
To address the 'memory wall' challenge, on-chip memory stacking has been proposed as a pro...
Abstract—A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can opera...
To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb ...
Abstract: A family of multi-die DRAM packages was developed that incorporate the full functionality ...
[[abstract]]To address the “memory wall” challenge, on-chip memory stacking has been proposed as a p...
Die stacking using Through Silicon Vias (TSVs) is a promising path for short, dense, and low capacit...
Megabit DRAM power supply is described in terms of power dissipation, reliability for small transist...
In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for ...
A leading edge 130 mn generation logic technology with 6 layers of dual damascene Cu interconnects i...
3D TSV (through silicon via) technologies promise increased system integration at lower cost and red...
Mobile DRAM is widely employed in portable electronic devices due to its fea-ture of low power consu...
none8Convergence of communication, consumer applications and computing within mobile systems pushes ...
Abstract—In recent few years, low-power electronics has been a leading drive for technology developm...
none43D integration based on TSV (through silicon via) technology enables stacking of multiple memor...
A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-mu...
To address the 'memory wall' challenge, on-chip memory stacking has been proposed as a pro...
Abstract—A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can opera...
To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb ...
Abstract: A family of multi-die DRAM packages was developed that incorporate the full functionality ...
[[abstract]]To address the “memory wall” challenge, on-chip memory stacking has been proposed as a p...
Die stacking using Through Silicon Vias (TSVs) is a promising path for short, dense, and low capacit...
Megabit DRAM power supply is described in terms of power dissipation, reliability for small transist...
In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for ...
A leading edge 130 mn generation logic technology with 6 layers of dual damascene Cu interconnects i...
3D TSV (through silicon via) technologies promise increased system integration at lower cost and red...