In high level synthesis, module selection, scheduling, and resource binding are inter-dependent tasks. For a selected module set, the best schedule/binding should be generated in order to accurately assess the quality of a module selection. Exhaustively enumerating all module selections and constructing a schedule and binding for each one of them can be ex-tremely expensive. In this paper, we present an iterative framework, calledWiZard to solve module selection problem under resource, latency, and power constraints. The framework associates a utility measure with each module. This measurement re ects the usefulness of the module for a given a design goal. Using modules with high utility values should result in superior designs. We propose ...
Clock selection has a significant impact on the performance and quality of designs in high-level syn...
During behavioural synthesis, an abstract functional description of a system is mapped automatically...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...
This paper proposes a new module selection algorithm for high-level synthesis. The algorithm uses an...
One of the most compelling reasons for developing highlevel synthesis systems has been the desire to...
While technology scaling has presented many new and exciting opportunities, new design challenges ha...
An integral challenge in synthetic circuit design is the selection of optimal parts to populate a gi...
Abstract—Increasing delay and power variation are significant chal-lenges to the designers as techno...
This paper describes a technique to integrate the three major tasks of high-level synthesis (schedul...
Module selection is a basic architectural synthesis task that allows to optimise the cost of the ded...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...
In this paper, we propose a design exploration framework for architectural synthesis which can handl...
In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as...
Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same desig...
ABSTRACT: An integral challenge in synthetic circuit design is the selection of optimal parts to pop...
Clock selection has a significant impact on the performance and quality of designs in high-level syn...
During behavioural synthesis, an abstract functional description of a system is mapped automatically...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...
This paper proposes a new module selection algorithm for high-level synthesis. The algorithm uses an...
One of the most compelling reasons for developing highlevel synthesis systems has been the desire to...
While technology scaling has presented many new and exciting opportunities, new design challenges ha...
An integral challenge in synthetic circuit design is the selection of optimal parts to populate a gi...
Abstract—Increasing delay and power variation are significant chal-lenges to the designers as techno...
This paper describes a technique to integrate the three major tasks of high-level synthesis (schedul...
Module selection is a basic architectural synthesis task that allows to optimise the cost of the ded...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...
In this paper, we propose a design exploration framework for architectural synthesis which can handl...
In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as...
Since manufacturing processes inherently fluctuate, LSI chips which are produced from the same desig...
ABSTRACT: An integral challenge in synthetic circuit design is the selection of optimal parts to pop...
Clock selection has a significant impact on the performance and quality of designs in high-level syn...
During behavioural synthesis, an abstract functional description of a system is mapped automatically...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...