Performance Evaluation of VLSI Platforms Using SystemQ

Abstract: Modern VLSI systems exhibit increasing complexity. The size of a design not only grows, but the system architecture also becomes more and more heteroge-neous and parallel. A key factor for a successful implementation is modeling and simulation of the design. However, modeling at register-transfer level (RTL) is not feasible anymore as a starting point. Already in the concept phase of a design quan-titative estimations of the system’s performance are required. To effectively support system engineers during this design phase we have developed a performance evalua-tion framework called SystemQ. By starting with a performance model we show how the system’s behavior and structure can be refined systematically. SystemQ is imple-mented in SystemC and seamlessly supports the refinement of performance models down to transaction level and RTL.