Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit

Abstract—This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector’s front-end sampler, and intersymbol interference in the system’s channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are di-rectly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12 % of an Hspice simulation—but with a simulation speed that is 1800 times higher. Index Terms—Clock jitter, clock-and-data recovery (CDR) mod-eling, discrete-time simulation, event driven. I