Design of Approximate Multiplier for Error-Tolerant Applications

CMOS scaling has reached to the level, where process variation has become significant problem hindering further scaling. Various approaches to mitigate process variation effect try to nullify at the cost of increased area/power consumption. There are some applications which accept small errors such as multimedia processing. Designing accurate circuit for these applications is waste of area/power. This paper proposes low power, high speed approximate multiplier. The proposed multiplier outperforms and provides significant improvement in power, area, and delay at the cost of little degrade in accuracy. Experimental result shows that the proposed multipliers consume less power and require less area compared to conventional truncated multiplier