A Distributed FIFO Scheme for on Chip Communication

Abstract — Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasitic effects. On chip communication now requires multiple clock cycles for signal propagation between communicating modules/components. Repeater insertion is widely used to improve global interconnect delays. We propose having distributed first in first out buffers to facilitate communication between components/modules of highly integrated systems, such as system on chip. This stateful scheme has very good tolerance for voltage and temperature variations. The buffer control circuitry is self-timed and allows for ease of interfacing in multiple domain clock designs. In this paper, we present the buffer and its associated control circuits that allow data transfers at a maximum frequency of 1.67 GHz in a 0.25 m technology