The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study

As DRAM cells continue to shrink, they become more susceptible to retention failures. DRAM cells that permanently exhibit short retention times are fairly easy to identify and repair through the use of memory tests and row and column redundancy. However, the retention time of many cells may vary over time due to a prop-erty called Variable Retention Time (VRT). Since these cells inter-mittently transition between failing and non-failing states, they are particularly difficult to identify through memory tests alone. In ad-dition, the high temperature packaging process may aggravate this problem as the susceptibility of cells to VRT increases after the as-sembly of DRAM chips. A promising alternative to manufacture-time testing is to detect and mitigate retention failures after the sys-tem has become operational. Such a system would require mecha-nisms to detect and mitigate retention failures in the field, but woul