Design of 6-T SRAM Cell for enhanced read/write

Abstract: SRAM is the most widely used embedded memory in modern digital systems, and their role is preferentially increasing. For all local storing purposes (registers, cache memory etc.), SRAM is the best solution because of its high speed since digital design can run at very high speed as compared to the access time of SRAM. Hence there is always need of increasing the speed of SRAM. This paper present an analysis of the Read / Write timings of SRAM using 6-T SRAM Cell, a latch-based Sense Amplifier and other peripheral circuitry in 90nm CMOS Technology. Based on the need to improve Access time in Read operation, which takes more time than write operation, a new design is proposed in which two Sense Amplifiers are used in each column of SRAM array. Each column of SRAM array is split into two equal portions and separate sense amplifiers are used in both the portions keeping the write driver same for both the parts which reduces the time of Read operation by around 50%. A control circuitry is used to enable the sense amplifiers one at a time according to the column address. The design netlist was generated using ORCAD tool and the simulation was done using spice models. However, there is a marginal increment in the area due to additional sense amplifiers used in the proposed design. It has been shown that the proposed design would improve the time of read operation without compromising with the power