Add to ORKGThis paper describes a new CAD tool, FTROM — Fault-Tolerant ROM compiler, which synthesizes layout geometries of fault-tolerant ROM modules with ßexible, user-speciÞed geometry and CMOS design-rule parameters. This physical design tool produces high-quality built-in self-testable (BIST) and fault-tolerant ROM layouts and uses a novel, minimum-delay overhead approach for fault-tolerance. A tool like FTROMeliminates the high cost of external testing of embedded ROM macros with I/O pins that are diƒcult to control and observe. ( 1998 Published by Elsevier Science B.V. All rights reserved
Fault-tolerance in integrated circuits is no longer the exclusive concern of space designers or high...
Abstract: Redundancy based hardening techniques are applied at the pre-synthesis or synthesis level....
The FTMPS-project provides a solution to the need for faulttolerance in large systems . A complete ...
This research focuses on a CAD tool, BISRAMGEN, that synthesizes layout geometries of built-in self-...
ISBN: 0818675454Fault tolerance has become a major concern in the design of VLSI systems. It is espe...
It is demonstrated that optimization techniques incorporated within a silicon compiler for read-only...
[[abstract]]The paper presents a prototype re-configurable tester for memory chips. The new tester c...
Abstract- Embedded RAMs are those whose address, data, and read/write controls cannot be directly co...
Increased systems level integration has meant the movement of many traditionally off chip components...
[[abstract]]Memory cores (especially SRAM cores) used on a system chip usually come from a memory co...
With continued scaling of silicon process technology, producing reliable electronic components in ex...
Summarization: This paper proposes a novel SRAM based FPGA architecture that is suitable for mapping...
De nos jours, les circuits FPGAs à base de mémoire SRAM sont omniprésents dans les applications élec...
ISBN 0-7803-9038-5International audienceIn modern SoCs embedded memories include the large majority ...
As processor manufacturers keep pushing the limits of the transistor, the reliability of computer sy...
Fault-tolerance in integrated circuits is no longer the exclusive concern of space designers or high...
Abstract: Redundancy based hardening techniques are applied at the pre-synthesis or synthesis level....
The FTMPS-project provides a solution to the need for faulttolerance in large systems . A complete ...
This research focuses on a CAD tool, BISRAMGEN, that synthesizes layout geometries of built-in self-...
ISBN: 0818675454Fault tolerance has become a major concern in the design of VLSI systems. It is espe...
It is demonstrated that optimization techniques incorporated within a silicon compiler for read-only...
[[abstract]]The paper presents a prototype re-configurable tester for memory chips. The new tester c...
Abstract- Embedded RAMs are those whose address, data, and read/write controls cannot be directly co...
Increased systems level integration has meant the movement of many traditionally off chip components...
[[abstract]]Memory cores (especially SRAM cores) used on a system chip usually come from a memory co...
With continued scaling of silicon process technology, producing reliable electronic components in ex...
Summarization: This paper proposes a novel SRAM based FPGA architecture that is suitable for mapping...
De nos jours, les circuits FPGAs à base de mémoire SRAM sont omniprésents dans les applications élec...
ISBN 0-7803-9038-5International audienceIn modern SoCs embedded memories include the large majority ...
As processor manufacturers keep pushing the limits of the transistor, the reliability of computer sy...
Fault-tolerance in integrated circuits is no longer the exclusive concern of space designers or high...
Abstract: Redundancy based hardening techniques are applied at the pre-synthesis or synthesis level....
The FTMPS-project provides a solution to the need for faulttolerance in large systems . A complete ...