A reconfigurable parallel signature analyzer for concurrent error correction in DRAM

Abstract-An efficient strategy to utilize a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAM’S is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log, w + 2 in the conventional Hamming code. Such an error-correction circuit (ECC) significantly improves the reliability of the memory system. I