Using Self-Adjustable Voltage Level Technique

In present scenario, an increasing demand for mobile electronic devices such as cellular phones, laptop computers and personal digital assistants requires the use of power efficient circuits. To minimize the power dissipation and to increase the battery lifetime, the supply voltage, VDD has been scaled down continuously. So, scaling down the supply voltage, without scaling down the threshold voltage increases the propagation delay. However the threshold voltage scaling results in substantial increases of sub-threshold leakage current, which increases the leakage or static power dissipation of the circuits. Therefore, the main aim of this work is to minimize the power dissipation by reducing leakage power. In this work, some of the combinational and sequential circuits are designed with CMOS transistors using self-Adjustable Voltage Level (SAL) technique to optimize the power dissipation. The circuits are implemented using the Mentor Graphics Backend Tool to analyze the power dissipation. With this SAL technique less than 50 % of the power dissipation can be reduced for designed circuits which lead to improve performance of the circuits