The system verification methodology for advanced TLM verification

The IEEE-1800 SystemVerilog [20] system description and verification language integrates dedicated verification fea-tures, like constraint random stimulus generation and func-tional coverage, which are the building blocks of the Univer-sal Verification Methodology (UVM) [3], the emerging stan-dard for electronic systems verification. In this article, we introduce our System Verification Methodology (SVM) as a SystemC library for advanced Transaction Level Modeling (TLM) testbench implementation. As such, we first present SystemC libraries for the support of verification features like functional coverage and constrained random stimulus gen-eration. Thereafter, we introduce the SVM with advanced TLM support based on SystemC and compare it to UVM and related approaches. Finally, we demonstrate the appli-cation of our SVM by means of a testbench for a two wheel self-balancing electric vehicle