Automatic Test Generation For Digital Circuits

ABSTRACT: Current VLSI manufacturing processes suffer from larger defective parts ratio, partly due to numerous emerging defect types. While traditional fault models, such as the stuck at and transition delay fault models are still widely used, they have been shown to be inadequate to handle these new defects. The main aim is to develop a complete behavioral fault simulation and automatic test pattern generation (ATPG) system for digital circuits modeled in verilog and VHDL. An integrated Automatic Test Generation (ATG) and Automatic Test Executing/Equipment (ATE) system for complex boards is developed here. An ATG technique called Behavior-Based Automatic Test Generation technique (namely BBATG) is developed. BBATG uses the device behavior fault model and represents a circuit board as interconnection of devices. The other method used here is novel test pattern generator (TPG) for built-in self-test. A multiplexer is developed to generate a class of minimum transition sequences. The entire hardware is realized as digital logical circuits and the test results are simulated in Xilinx and Model sim software. Gate level simulation is not an effective solution for complex microcircuits. The low cost, versatile and reconfigurable FPGA-based ATE is implemented called FATE to support in ASIC development phase. The results of this research show that behavioral fault simulation will remain as a highly attractive alternative for the future generation of VLSI and system-on-chips (SoC)