The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits

computing devices inspired by the structure and functioning of neural cells. The presence of unreliable components in SN P systems can be considered in many different aspects. In this paper we focus on two types of unreliability: the stochastic delays of the spiking rules and the stochastic loss of spikes. We propose the implementation of elementary SN P systems with DRAM-based CMOS circuits that are able to cope with these two forms of unreliability in an efficient way. The constructed bio-inspired circuits can be used to encode basic arithmetic modules. 1 Reliability and SN P Systems Membrane computing (known also as P systems) is a model of computation in-spired by the structure and the functioning of living cells, [8]. A P system is a parallel computing device based on multiset rewriting in compartments where a global clock is assumed and each rule of the system is executed in one time step. Spiking neural P systems (in short, SN P systems) have been introduced as com-puting devices inspired by the structure and functioning of neural cells (a friendly introduction to this model of computation is given in [7] while a more complete review is provided in the corresponding chapter of the handbook, [8]). The main idea of an SN P system is to have several one-membrane cells (called neurons) which can hold any number of spikes; each neuron fires (spikes) in spec-ified conditions (after accumulating a specified number of spikes). In the basi