Minimization of Dynamic Power using Pulsed Latch for Clock Tree

Abstract: Nowadays power consumption is an important issue in high-performance digital circuits. Reducing the size of a clock tree is an effective approach to reduce dynamic power dissipation in digital circuit designs. Existing methods are based on reduction of the flip-flop power alone, which gives limited amount of power saving. To achieve the considerable power saving, this paper gives an analysis of the pulsed- latch utilization in a clock tree. This is the first step to propose a novel approach to efficiently construct a clock tree with both pulsed-latches and flip-flops. The proposed method is based on minimum-cost, maximum-flow formulation to determine the tree topology. It maintains load balance and considers the wire length between pulse generators and pulsed latches. Experimental results indicate that the proposed novel approach can reduce the power consumption by 25 % to 30 %.It is an average compared with the most recent paper on the industrial circuits and ISCAS-2012 benchmarks, respectively