Towards Checking Protocol Conformance of Active Components

As UML 2.x is now widely used by practitioners to document software architectures of concurrent real-time systems we propose an approach to make use of the UML protocol and behavior artifacts of components in order to achieve a verification activity at design time. We first discuss the issue of using protocol state machines to depict interactions of any active component with its environment through ports that specify provided and/or required interfaces. We propose to extend the use of such models to depict the flow of both asynchronous and synchronous events send not only from outside into the component but also in the other direction provided that the outgoing events affect the component state which is exposed to its environment via its ports. We then propose a formal method for conformance checking between component behavior and protocol state machines. These models are first mapped into abstract and flattened automata which are then combined and verified using model-checkers to uncover design flaws leading to deadlocks and race conditions in the implemented system. We explore also to what extent sequence diagrams could be suited over protocol state machines to annotate time constraints and how to use them for time consistency checking between implementation and specification models